Digital Input-Output (I/O) of MSP432P401R Microcontroller | In order you can using MSP432P401R microcontroller chip to build your own embedded systems application, you have to know about the detail features of this microcontroller chip and how to use its. On today article, I will try to explain for you about one important feature of the SimpleLink MSP432P401R microcontroller chip, i.e. Digital Input/Output (I/O). Understanding the I/O feature of this microcontroller chip is an important thing for you, without that, an embedded systems application using this microcontroller chip will not create properly and running well. 

Quote the explanation of MSP432P401R microcontroller digital I/O from its technical reference manual document (Pages 677), the digital I/O features include: 
  • Independently programmable individual I/Os 
  • Any combination of input or output 
  • Individually configurable interrupts for ports (available for certain ports only) 
  • Independent input and output data registers 
  • Individually configurable pullup or pulldown resistors 
  • Wake-up capability from ultra-low-power modes (available for certain ports only) 
  • Individually configurable high drive I/Os (available for certain I/Os only) 
Devices within the family may have up to eleven digital I/O ports implemented (P1 to P10 and PJ). Most ports contain eight I/O lines; however, some ports may contain less (see the device-specific data sheet for ports available). Each I/O line is individually configurable for input or output direction, and each can be individually read or written. Each I/O line is individually configurable for pullup or pulldown resistors. 

Certain ports have interrupt and wake-up capability from ultra-low-power modes (see device-specific data sheet for ports with interrupt and wake-up capability). Each interrupt can be individually enabled and configured to provide an interrupt on a rising or falling edge of an input signal. All interrupts are fed into an encoded interrupt vector register, allowing the application to determine which pin of a port has generated the event. 

Individual ports can be accessed as byte-wide ports or can be combined into half-word-wide ports. Port pairs P1 and P2, P3 and P4, P5 and P6, P7 and P8, and so on, are associated with the names PA, PB, PC, PD, and so on, respectively. All port registers are handled in this manner with this naming convention. The main exception are the interrupt vector registers, for example, interrupts for ports P1 and P2 must be handled through P1IV and P2IV, PAIV does not exist. 

When writing to port PA with half-word operations, all 16 bits are written to the port. When writing to the lower byte of port PA using byte operations, the upper byte remains unchanged. Similarly, writing to the upper byte of port PA using byte instructions leaves the lower byte unchanged. When writing to a port that contains fewer than the maximum number of bits possible, the unused bits are don't care. Ports PB, PC, PD, PE, and PF behave similarly. 

Reading port PA using half-word operations causes all 16 bits to be transferred to the destination. Reading the lower or upper byte of port PA (P1 or P2) and storing to memory using byte operations causes only the lower or upper byte to be transferred to the destination, respectively. When reading from ports that contain fewer than the maximum bits possible, unused bits are read as zeros (similarly for port PJ). 

1. MSP432P401R Microcontroller - I/O Pins Mapping 
Figure 1 and figure 2 show for you the Simplelink MSP432P401 microcontroller I/O pins mapping on the SimpleLink MSP432 development kit. 

2. MSP432P401R Microcontroller - Digital I/O Registers 
From the MSP432P401R microcontroller digital I/O technical reference manual document (Page 676-699), you will get information about the twelve digital I/O register. 

Figure 3. MSP432P401 microcontroller - Digital I/O registers 

The registers which will involved when you configure the digital I/O of MSP432P401 microcontroller: 

1. PxIV (Port X Interrupt Vector) Register 
2. PxIN (Port X Input) Register 
3. PxOUT (Port X Output) Register 
4. PxDIR (Port X Direction) Register 
5. PxREN (Port X Pullup or Pulldown Resistor Enable) Register 
6. PxDS (Port X Drive Strength Selection) Register 
7. PxSEL0 (Port X Function Selection) Register 0 
8. PxSEL1 (Port X Function Selection) Register 1 
9. PxSELC (Port X Complement) Selection 
10. PxIES (Port X Interrupt Edge Select) Register 
11. PxIE (Port X Interrupt Enable) Register 
12. PxIFG (Port X Interrupt Flag) Register 

Note X = 1, 2, 3, 4, 5, 6, 7, 8, 9 or 10 

3. MSP432P401R Microcontroller - Digital I/O Operation 
The digital I/O are configured with user software. The setup and operation of the digital I/O are discussed in the following sections. 

3.1 Input Registers (PxIN) 
Each bit in each PxIN register reflects the value of the input signal at the corresponding I/O pin when the pin is configured as I/O function. These registers are read only. 

• Bit = 0: Input is low 
• Bit = 1: Input is high 

3.2 Output Registers (PxOUT) 
Each bit in each PxOUT register is the value to be output on the corresponding I/O pin when the pin is configured as I/O function, output direction. 

• Bit = 0: Output is low 
• Bit = 1: Output is high 

If the pin is configured as I/O function, input direction and the pullup or pulldown resistor are enabled; the corresponding bit in the PxOUT register selects pullup or pulldown. 

• Bit = 0: Pin is pulled down 
• Bit = 1: Pin is pulled up 

3.3 Direction Registers (PxDIR) 
Each bit in each PxDIR register selects the direction of the corresponding I/O pin when it is configured for I/O function. PxDIR register also in most of the cases controls the direction of the I/O when it is configured for peripheral functions. PxDIR bits for I/O pins that are selected for peripheral functions must be set as required by the peripheral functions. For certain secondary functions like eUSCI, the I/O direction is controlled by the secondary function itself and not by the PxDIR register. Refer to device-specific data sheet for more details. 

• Bit = 0: Port pin is switched to input direction 
• Bit = 1: Port pin is switched to output direction 

3.4 Pullup or Pulldown Resistor Enable Registers (PxREN) 
Each bit in each PxREN register enables or disables the pullup or pulldown resistor of the corresponding I/O pin. The corresponding bit in the PxOUT register selects if the pin contains a pullup or pulldown. 

• Bit = 0: Pullup or pulldown resistor disabled 
• Bit = 1: Pullup or pulldown resistor enabled 

Table 1 summarizes the use of PxDIR, PxREN, and PxOUT for proper I/O configuration. 

Table 1. I/O configuration 

3.5 Output Drive Strength Selection Registers (PxDS) 
There are two type of I/Os available. One with regular drive strength and the other with high drive strength. Most of the I/Os have regular drive strength while some selected I/Os have high drive strength. See device-specific data sheet for the I/Os with high drive strength. PxDS register is used to select the drive strength of the high drive strength I/Os. 

• Bit = 0: High drive strength I/Os are configured for regular drive strength 
• Bit = 1: High drive strength I/Os are configured for high drive strength 

PxDS register does not have any effect on the I/Os with only regular drive strength. 

3.6 Function Select Registers (PxSEL0, PxSEL1) 
Port pins are often multiplexed with other peripheral module functions. See the device-specific data sheet to determine pin functions. Each port pin uses two bits to select the pin function – I/O port or one of the three possible peripheral module function. Table 2 shows how to select the various module functions. Each PxSEL bit is used to select the pin function – I/O port or peripheral module function 

Table 2. I/O function selection 

Setting the PxSEL1 or PxSEL0 bits to a module function does not automatically set the pin direction. Other peripheral module functions may require the PxDIR bits to be configured according to the direction needed for the module function. See the pin schematics in the device-specific data sheet. 

When a port pin is selected as an input to peripheral modules, the input signal to those peripheral modules is a latched representation of the signal at the device pin. While PxSEL1 and PxSEL0 is other than 00, the internal input signal follows the signal at the pin for all connected modules. However, if PxSEL1 and PxSEL0 = 00, the input to the peripherals maintain the value of the input signal at the device pin before the PxSEL1 and PxSEL0 bits were reset. 

3.7 Port Interrupts 
3.7.1 Interrupt Vector (PxIV) & Interrupt Flag (PxIFG) Register 
All Px interrupt flags for a particular port are prioritized, with PxIFG.0 being the highest, and combined to source a single interrupt vector. The highest priority enabled interrupt generates a number in the PxIV register. This number can be evaluated or added to the program counter to automatically enter the appropriate software routine. Disabled Px interrupts do not affect the PxIV value. The PxIV registers are half-word access only. 

Each PxIFG bit is the interrupt flag for its corresponding I/O pin, and the flag is set when the selected input signal edge occurs at the pin. All PxIFG interrupt flags request an interrupt when their corresponding PxIE bit is set. Software can also set each PxIFG flag, providing a way to generate a software-initiated interrupt. 

• Bit = 0: No interrupt is pending 
• Bit = 1: An interrupt is pending 

Only transitions, not static levels, cause interrupts. If any PxIFG flag becomes set during a Px interrupt service routine or after Px interrupt service routine execution is completed, the set PxIFG flag generates another interrupt. This ensures that each transition is acknowledged. 

Any access (read or write) of the PxIV register automatically resets the highest pending interrupt flag. If another interrupt flag is set, another interrupt is immediately generated after servicing the initial interrupt. 

For example, assume that P1IFG.0 has the highest priority. If the P1IFG.0 and P1IFG.2 flags are set when the interrupt service routine accesses the P1IV register, P1IFG.0 is reset automatically. After the completion of P1IFG.0 interrupt service routine, the P1IFG.2 generates another interrupt. 

3.7.2 Interrupt Edge Select Registers (PxIES) 
Each PxIES bit selects the interrupt edge for the corresponding I/O pin. 

• Bit = 0: Respective PxIFG flag is set on a low-to-high transition 
• Bit = 1: Respective PxIFG flag is set on a high-to-low transition 

Writing to PxIES for each corresponding I/O can result in setting the corresponding interrupt flags. 

Table 3. Writing to PxIES 

3.7.3 Interrupt Enable Registers (PxIE) 
Each PxIE bit enables the associated PxIFG interrupt flag. 
• Bit = 0: The interrupt is disabled 
• Bit = 1: The interrupt is enabled 

4. How To Configure The Digital I/O Using C Program 

Configure Px as output
P3->DIR = 0xFF;       // Configure all of P3 pins as output
P3->OUT = 0x00;       // All of P3 pins output is low

P4->SEL1 &= ~2;       // configure P4.1 as general-purpose I/O
P4->SEL0 &= ~2;
P4->DIR |= 2;         // P4.1 set as output pin

P5->SEL1 &= ~0x10;    // configure P5.4 as primary-module I/O
P5->SEL0 |= 0x10;
P5->DIR |= 0x10;      // P5.4 set as output pin

P6->SEL1 &= ~0x14;      // configure P6.2 & P6.4 as general-purpose I/O
P6->SEL0 &= ~0x14;
P6->DIR |= 0x14;        // P6.2 & P6.4 set as output pin
Configure Px as input
P1->DIR = 0x00;       // Configure all of P1 pins as input
P1->OUT = 0xFF;       // All of P1 input is pulled Up

P5->SEL1 &= ~2;       // configure P5.1 as general-purpose I/O
P5->SEL0 &= ~2;
P5->DIR  &= ~2;       // P5.1 set as input pin

P7->SEL1 &= ~0x10;    // configure P7.4 as primary-module I/O
P7->SEL0 |= 0x10;
P7->DIR  &= ~0x10;    // P7.4 set as input pins

P9->SEL1 &= ~0x14;      // configure P9.2 & P9.4 as general-purpose I/O
P9->SEL0 &= ~0x14;
P9->DIR  &= ~0x14;      // P9.2 & P9.4 set as input pins


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About Taufiq D.S. Suyadhi

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